1. Field of the Invention
The present invention relates to a data output controller for a memory device, and more particularly to a data output controller allowing data eyes to have the same width by adjusting a timing in which data are outputted from a synchronous memory device such as DDR SDRAM and DDR2 SDRAM.
2. Description of the Prior Art
FIG. 1 is a circuit view showing a typical data output controller used for a synchronous memory device.
For the purpose of description, description about functions of signals shown in FIG. 1 will be given before that of a data output controller operation.
RKDLL denotes an output signal of a Delay Locked Loop circuit used for a synchronous memory device such as DDR SDRAM and DDR2 SDRAM and has a negative delay with respect to an external clock signal (a signal CLK shown in FIG. 2). Data outputted from a memory device can be arranged in synchronization with the external clock signal by using the signal RCKDLL having a negative delay with respect to the external clock signal CLK. In more detail, the signal RCKDLL being an output clock of the DLL circuit has a negative delay with respect to the external clock signal CLK being a reference clock, and sends data outputted from the interior of the memory device at a time point in which the external clock signal is inputted.
ROUTEN denotes a window signal for determining the number of pulses of the signal RCKDLL for data output.
ROUTNE2 denotes a signal obtained by delaying the signal ROUTEN by a predetermined time.
RCK_DO_QS denotes a DLL clock signal for outputting a signal DQS and is outputted correspondingly to a burst length.
DQS denotes signal defined in a standard for DDR SDRAM or DDR2 SDRAM. This signal latches data at a write operation and is toggled to a high level/a low level while being aligned with data at a read operation.
It can be understood from FIG. 1 that the signal RCK_DO_QS controls timing at which a data buffer 106 and a DQS buffer 107 operate. In FIG. 1, although the data buffer 106 and the DQS buffer 107 are realized by using a D-flip/flop, this is an example for the purpose of description. Accordingly, those skilled in the art can realize various circuits for outputting data and the signal DQS in synchronization with a rising edge and a falling edge of the signal RCK_DO_QS.
FIG. 2 is a signal timing chart for explaining an operation of the data output controller shown in FIG. 1. Hereinafter, description about a case in which “CL=6” and “BL=8” in a memory device will be given with reference to FIG. 2. For reference, in FIG. 2, ‘N’ of ‘DQ<1:N>’ indicates the number of input/output data pins, and each input/output pin sequentially outputs eight data. Herein, the CL denotes CAS latency.
A read command is applied in synchronization with a rising edge of a pulse marked as ‘0,0’ of the external clock signal (CLK) in FIG. 2. Since ‘CL’ is equal to six, data are outputted in synchronization with a rising edge of a sixth pulse of the external clock signal CLK (the rising edge of a pulse marked as ‘6.0’ of the external clock signal) after the read command is applied.
As described above, the internal clock signal RCKDLL is a signal outputted from the DLL circuit and has a negative delay with respect to the external clock signal CLK. FIG. 2 shows a negative delay in which the internal clock signal RCKDLL leads about one clock pulse over the external clock signal CLK.
As noted from FIG. 2, the signal RCK_DO_QS is a signal outputted through an AND operation of the signal ROUTEN2 and the signal RCKDLL during a high level of the signal ROUTEN2.
As noted from FIGS. 1 and 2, the signal DQS and the data signal DQ are outputted in synchronization with a rising edge and a falling edge of the signal RCK_DO_QS.
However, as noted from FIG. 2, the state of a first pulse of the signal DQS is changed to a logic high from a logic low, and the state of a first pulse of the data signal is changed into a logic high or a logic low from a high impedance state having ½VCC. For this reason, a duration for output of the first data is greater an interval of ‘t1’ than each of durations for output of the remaining seven data which are outputted subsequently to the first data. Herein, the ‘t1’ means a time in which the state of the output port of the data output buffer (reference numeral 106 shown in FIG. 1) is changed into a low impedance state from a high impedance state. In this case, the high impedance state refers to a state in which the data output buffer is not operated, and the low impedance state refers to a state in which the data output buffer is normally operated. Such a time ‘t1’ is called “tLZ (Data Low Impedance time)”. It is problematic that the conventional memory device has an unstable tLZ.
Data eyes of sequentially outputted data have different widths due to this timing difference, tLZ. In other words, as shown in FIG. 2, a data eye of the first data is different from data eyes of the second data to the eighth data.
Also, when a plurality of memory devices share a common data bus and data are subsequently outputted from at least two memory devices, an instantaneous short may occur between a voltage source and ground during the ‘t1’. In other words, if the last data of the first memory device has a high state and the first data of the second memory device has a low state, the interval ‘t1’ may connect the logics of ‘High’ and ‘Low’ to each other, thereby causing short-circuiting. Such an instantaneous short may make a memory device or PCB board unstable and cause damage of a power circuit.